The T2316162A is a randomly accessed solid state memory containing 16,777,216 bits organized in a x16 configuration. The T2316162A has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. It offers Fast Page mode with Extended Data Output.
The T2316162A CAS function and timing are determined by the first CAS to transition low and by the last to transition back high. Use only one of the two CAS and leave the other staying high during WRITE will result in a BYTE WRITE. CASL transiting low in a WRITE cycle will write data into the lower byte (DQ0~DQ7), and CASH transiting low will write data into the upper byte (DQ8~DQ15).
The T2316162A CAS function and timing are determined by the first CAS to transition low and by the last to transition back high. Use only one of the two CAS and leave the other staying high during WRITE will result in a BYTE WRITE. CASL transiting low in a WRITE cycle will write data into the lower byte (DQ0~DQ7), and CASH transiting low will write data into the upper byte (DQ8~DQ15).
Features
- Industry-standard x 16 pinouts and timing functions.
- Single 5V (±10%) power supply.
- All device pins are TTL-compatible.
- 1K-cycle refresh in 16ms.
- Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN.
- Extended data-out (EDO) PAGE MODE access cycle.
- BYTE WRITE and BYTE READ access cycles.
Main Products
DRAM