The T2316402A is randomly accessed solid state memory containing 16,777,216 bits organized in a x 4 configuration. It offers Fast Page mode with Extended Data Output (EDO).
During READ or WRITE cycles, each of the 4 memory bits (1 bit per I/O) is uniquely addressed through the 22 address bits, which are entered 11 bits (A0-A10) at a time. RAS latches the first 11 bits and CAS latches the latter 11 bits.
A READ or WRITE cycle is selected with the WE input. A logic HIGH on WE dictates READ.
During READ or WRITE cycles, each of the 4 memory bits (1 bit per I/O) is uniquely addressed through the 22 address bits, which are entered 11 bits (A0-A10) at a time. RAS latches the first 11 bits and CAS latches the latter 11 bits.
A READ or WRITE cycle is selected with the WE input. A logic HIGH on WE dictates READ.
Features
- Industry-standard x 4 pinouts and timing functions.
- Single 5V (±10%) power supply.
- All device pins are TTL-compatible.
- 2048-cycle refresh in 32 ms.
- Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN.
- Extended data-out(EDO) PAGE MODE access cycle.
Main Products
DRAM