The Taiwan Memory Technology Synchronous Burst RAM family employs high-speed, low power CMOS design using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The T3512864A SRAM integrates 131072 x 64 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, three active LOW chip enable (CE,CE2 and CE3), two additional chip enables (CE2 and CE3), burst control inputs.
Features
- Fast Access times: 4.0, 4.2, 4.5 and 5ns
- Fast clock speed: 133, 125, 117 and 100MHz
- Provide 3-1-1-1 burst access
- Fast OE access times: 3.8 and 4.0ns
- Single 3.3V +10% / -5% power supply
- BYTE WRITE ENABLE and GLOBAL WRITE control
- Five chip enables for depth expansion and address pipelining
- Address, control, input and output pipelined registers
- Intemally self-timed WRITE cycle
- WRITE pass-through capability
- Burst control pins (interleaved or liner burst sequence)
- High density, high speed packages
- Low capacitive bus loading
- High 30pF output drive capability at rated access time
- SNOOZE MODE for reduced power standby
Main Products
DRAM